Game-Changing Redesign of Restart and Trunk Circuits of Battery Management System (BMS) for Enhanced Performance

The challenge at hand emerged when our client encountered functionality issues with the existing circuit design, specifically within the BMS module on SBC1, failing to meet updated requirements.

Here’s an insight into the intricate details of our approach to addressing these challenges with precision and innovation.

Wake-Up Recognition

For Restart:

The circuit must accurately identify signals of at least 8V @ 100ms as High, prompting a wake-up response.

This entails the implementation of a latch circuit for pulse input signal and digital input for the signal at the end of the latch circuit.

For Trunk:

It is essential for the circuit to recognize signals as LOW from a minimum value of 2.2V or higher, requiring wake-up initiation. Only pulse signals longer than 20ms should activate recognition. Similar to the Restart phase, this involves implementing a latch circuit and digital input for the signal.

Approach and Methodology

Our Statement of Work (SOW) encompasses a multi-faceted approach, including.

Identifying Reason for Failure

This involves an exhaustive analysis of the existing design, comprehensive results discussion, and meticulous component sourcing.

Circuit Design Phase

This phase encompasses an in-depth exploration of the proposed circuit design, detailed analysis & calculation, and thorough documentation.

Existing Design Analysis

The existing circuit design relies on discrete components to regulate the voltage usable by the pin of SBC1. Notably, there is no introduction of delay by the programmed SBC1, resulting in functional limitations.

Result & Discussion

After meticulous analysis, it was discerned that the SBC1 encounters challenges in creating a delay when the input signal is analog and experiences a sudden rise in voltage.

Component Sourcing

Our component sourcing process involved careful selection from reputable suppliers such as TI, Analog Devices, and RoHM, culminating in the identification of TI’s TPS37-Q1 as the ideal solution due to its internal voltage divider configuration and dual adjustable time delay.

Proposed Circuit Design

TPS37x Chip Integration for RESTART Wakeup Detection

The TPS37x chip plays a pivotal role in enabling the generation of RESET when the voltage level reaches 8V @ 100ms, aligning seamlessly with the stringent RESTART wakeup detection requirement. This feature represents a significant advancement in circuit design, elevating the performance and responsiveness of the system.

Furthermore, the integration of the TPS37x chip empowers the circuit to reset the latch through the GPIO signal from the MCU1-RESTART_LATCH, ushering in a streamlined and synchronized operation that underscores the efficacy of the revamped design.

TPS37x Chip Integration for TRUNK Wakeup Detection

Elevating the standards of TRUNK wakeup detection, the TPS37x chip facilitates the generation of RESET when the voltage level surpasses 2.2V @ 20ms, aligning flawlessly with the requisite functionality on SBC1. This integration represents a paradigm shift in circuit design, fortifying the system’s ability to detect TRUNK signals with unparalleled precision and reliability.

Moreover, the circuit’s ability to reset the latch through the GPIO signal from the MCU1-TRUNK_LATCH underscores the seamless synergy between hardware and software components, culminating in a harmonized and responsive system architecture.

Proposed Design Calculations and Analysis Setup

The analysis involved simulating the circuit at three distinct voltages (8V,

9V, and 16V) while maintaining a consistent delay configuration within

The integrated circuit (IC).

Proposed Design Validation Result and Value Add

In-depth simulations were conducted across varied voltage levels to validate the proposed design, resulting in a robust and reliable solution that surpasses the existing design.

Value Adds

This particular output not only meets their specific requirements for the circuit and delay, but also exceeds the capabilities of the existing design, thereby significantly enhancing the overall value of the Battery Management System (BMS).